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Improved Noise Performance of MOSFET Gate Drain Charge sharing at node capacitance

Author(s):

Apna Joshi , S.I.R.T.-Bhopal; Reenav Shukla, S.I.R.T.-Bhopal; Himanshu Nautiyal, S.I.R.T.-Bhopal

Keywords:

MOSFET, Drain Charge, CMOS

Abstract

This paper work is focused on problems of process variations; timing, noise tolerance, and power are investigated together for performance optimization. The existing techniques for suffer from one or more of the following shortcomings: slow speed and vulnerability to fast trapping, VD dependence, cable-changing, sensitivity to gate leakage, complex procedure, and a need for modelling or simulation. Here we can design the dynamic CMOS circuit. Dynamic logic circuits use for design of wide fan in logic gates with less number of transistors and large speed as compare of static CMOS gates. But these circuits are not susceptible to noise. Noise in digital integrated circuits refers to any phenomenon that causes the voltage fluctuations at a node from its nominal value. Of the several logic styles available, dynamic CMOS logic has been predominantly used in VLSI circuits, and their usage has increased the timing performance significantly over static CMOS circuits. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect.

Other Details

Paper ID: IJSRDV2I1014
Published in: Volume : 2, Issue : 1
Publication Date: 01/04/2014
Page(s): 48-49

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