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VHDL Implementation Of 8-Bit Vedic Multiplier Using Barrel Shifter


Bhavin D Maru , C.U.Shah College of Engineering & Technology; Prof.Altaf Darvadiya, C.U.Shah College of Engineering & Technology


Vedic Formulas, Nikhilam Sutra, Barrel Shifter, Base Selection Module, Propagation Delay, Power Index Determinant.


This paper describe that the propagation delay of 8-bit Vedic multiplier is reduced when compared with conventional multiplier like array multiplier, booth multiplier, wallance multiplier.in our design we use barrel shifter which requires only one clock cycle for 'n' number of shifts. The design is implemented in Xilinx simulator and verified using ISE simulator. The design will implement on Xilinx Spartan-6 family. The propagation delay will take from synthesis report and static timing report. The design may achieve propagation delay approximately 6ns to 9ns using barrel shifter in base selection module and multiplier.

Other Details

Paper ID: IJSRDV2I1035
Published in: Volume : 2, Issue : 1
Publication Date: 01/04/2014
Page(s): 156-158

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