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Performance analysis of sigma delta ADC using 45nm CMOS Technology


Arpit R Patel , L.J.Institute Of Technology


Discrete Time Sigma Delta Modulator, Decimation Filter.


We report a new architecture for a sigma delta oversampling analog to digital Convertor (ADC) in which the first order sigma delta modulator and second order Decimation Filter is designed in 45nm CMOS technology. In this work, both modulator and decimation filter is designed with the software LTspice. The sigma delta modulator is designed using Switch Capacitor Integrator and comparator with an 8 MHz sampling clock frequency. The decimator is designed using a second order Cascaded Integrator Comb (CIC) filter and can be worked with two different oversampling ratios of 64 and 16. The input to the decimator is provided from a first order modulator. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit. The Sigma Delta ADC can be operated with an oversampling clock frequency of up to 8 MHz and with an input signal bandwidth of up to 65 KHz. An inbuilt clock divider circuit has been designed which generates two output clocks whose frequencies are equal to the input clock frequency divided by the oversampling ratios 64 and 16.

Other Details

Paper ID: IJSRDV2I1078
Published in: Volume : 2, Issue : 1
Publication Date: 01/04/2014
Page(s): 80-83

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