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Power and Area Efficient Full Adder Design using High Performance CMOS Technology


Shagun Sharma , Galaxy Global Educational Trust's Group of Institutions; Er. Ankita Mittal, Galaxy Global educational trust's group of institutions


Full adder, CMOS gates, Transistor logics, Sum, Carry


This paper presents the realization of full adder designs using Complimentary CMOS Design, Complimentary Pass Transistor Logic Design. The main motive of this paper is to determine the comparative study of power, surface area and complexity of Full adder designs using CMOS Logic Styles. The conventional design consists of 28 transistors and proposed design consists of 10 transistors. Simulations results clearly determine that proposed Full adder Design is better compared to conventional design. Transistor Design with respect to power, delay, Power Delay Product Comparison.

Other Details

Paper ID: IJSRDV2I12010
Published in: Volume : 2, Issue : 12
Publication Date: 01/03/2015
Page(s): 3-6

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