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Power Reduction in the VLSI Architecture of FM0 and Manchester Encoding


J. Rasathi , prathyusha institute of technology and management; S. M. Subramanian, prathyusha institute of technology and management; N. Nagaraj, prathyusha institute of technology and management; R. Ajin, prathyusha institute of technology and management


DSRC, VLSI architecture, FM0 Encoding


Power is a major problem faced by all electronic and electrical circuits designed in these days. The main objective of this work is to combine the VLSI architecture of FM0 and Manchester encoding so that it reduces the power used, by reducing the number of components used and improves the performance of the FM0 and Manchester encoding. These results are observed using spice. The power consumed is 0.72 mw for Manchester encoding. The power consumption is 0.14 mw for FM0 encoding. The FM0 and Manchester encoding is used widely in dedicated short range communication. Signal reliability could be achieved in dedicated short range communications by adopting FM0 and Manchester encoding. The transportation system in these days relies upon dedicated short range communication (DSRC). Many countries around the world depend on DSRC standards. Europe, Japan is the major countries which rely upon dedicated short range communication.

Other Details

Paper ID: IJSRDV2I12063
Published in: Volume : 2, Issue : 12
Publication Date: 01/03/2015
Page(s): 861-864

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