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Dynamic Voltage Scaling Multiplier Using Twin-Precision Technique for Low Power Design

Author(s):

Mythili C , KALAIGNAR KARUNANIDHI INSTITUTE OF TECHNOLOGY; S.Chandrakala, KALAIGNAR KARUNANIDHI INSTITUTE OF TECHNOLOGY

Keywords:

twin precision multiplier, dynamic voltage scaling (DVS), parallel processing (PP), razor flip-flops

Abstract

The flexible twin-precision multiplier is combined with variable precision, parallel processing (PP), Razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for different operating conditions. The twin-precision technique can reduce the power dissipation by adapting a multiplier to the bit width of the operands being computed. The technique also enables an increased computational throughput, by allowing several narrow-width operations to be computed in parallel. All of the building blocks of proposed flexible twin-precision multiplier can either work as independent small precision multiplier or parallel to perform higher-precision multiplier. While still maintain the full through-put, the dynamic voltage and frequency scaling management unit configures the twin-precision multiplier to operate at the proper precision and frequency. Adapting to the run-time workload for targeted application, that flexible multiplier can used to design for DSP application. Razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage margin and overhead typically associated to DVS to lowest level. Finally, the proposed high speed flexible twin-precision multiplier, can further benefits from an operand scheduler that rearranges the input data, hence determine the optimum voltage and frequency operating conditions for minimum power and delay consumption. This architecture is simulated and results are obtained using TANNER EDA 13, MODEL SIM 10.1b and XILINX ISE tool.

Other Details

Paper ID: IJSRDV2I12358
Published in: Volume : 2, Issue : 12
Publication Date: 01/03/2015
Page(s): 804-808

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