High Impact Factor : 4.396 icon | Submit Manuscript Online icon |

Modeling and Analysis of design in MTCMOS layout in VDSM

Author(s):

R R Raghunaath , Muthayammal engineering college; A Lalithakumar, Muthayammal engineering college

Keywords:

MTCMOS, Switched Bank circuit, CMOS buffer, 32nm, VDSM, Delay, Power consumption, Area.

Abstract

For low power design supply voltages and threshold voltages are reduced with advanced 35nm CMOS technology. Lowering the threshold voltage introduces the increase in leakage current. This technique disconnects the low Vth switching block from power supply line and ground line by cutting off high Vth sleep transistors whenever circuit is in idle mode. In this paper, we present a multi threshold CMOS technique to reduce the leakage current as well as it controls the ground bounce noise. This was done by using changing of CMOS design to tri-state MTCMOS transistor. In an MTCMOS circuit, high threshold voltage (high-|Vth|) sleep transistors (header and/or footer) are used to cut off the power supply and/or the ground connections to an idle low threshold voltage (low-|Vth|) circuit block. The propagation delay and the dynamic switching power consumption of active logic blocks can be thereby increased. Multiple autonomous power and ground gated circuit domains are typically utilized for effective control of leakage power consumption in MTCMOS circuits. This is enhanced version of MTCMOS technique to suppress the ground bounce noise. A further high Vth PMOS called Dozer is connected in parallel with footer sleep transistor. The new model, verified by TANNER simulations and measured data, includes delay, area and low power consumption result shows the better performance rate of this proposed system and also make that in 32nm size with that application of Switched Bank circuit.

Other Details

Paper ID: IJSRDV2I2191
Published in: Volume : 2, Issue : 2
Publication Date: 01/05/2014
Page(s): 303-307

Article Preview

Download Article