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Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology

Author(s):

Sunil R. Gupta , Faculty Of Engineering, Shree Saraswati Edu. Sansthan Group Of Institutions, Rajpur, Kadi; Pratik P. Shah, Faculty Of Engineering, Shree Saraswati Edu. Sansthan Group Of Institutions, Rajpur, Kadi

Keywords:

SRAM, Sense amplifier, Cross coupled Voltage mode sense amplifier, Current latched sense amplifier , Current sense amplifier

Abstract

In this paper voltage mode sense amplifier, current latch sense amplifier and c urrent sense amplifier is analyzed and simulated with and without MTCMOS technique in a 45nm process technology using Ngspice circuit simulator. When density of memory is increased, the bit line capacitance is also increases and due to that, it limits the speed of voltage sense amplifier. To overcome this problem current sense amplifier is used, which is not dependent on bit line capacitance. This paper shows that delay time is reduced in current sense amplifier compare to voltage mode sense amplifier and current latch sense amplifier but power consumption is increased. MTCMOS technique is used to reduce power dissipation.

Other Details

Paper ID: IJSRDV2I2192
Published in: Volume : 2, Issue : 2
Publication Date: 01/05/2014
Page(s): 229-233

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