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System Verilog based Verification of Write Operation in SDRAM using Memory Controller


Sandeep Raval , GTU PG School, Ahmedabad


SDRAM, Verification, System Virology, Modelsim 6.3f, Write Operation


In this paper, a Write Operation is done into the SDR SDRAM using Memory Controller that is verified. Basically as the memory, the basic Write and Read operation is performed to it. To see this Functionality working correctly, it needs to be verified. For this the Verification Environment is to be created. The Interface, Program Block, Generator, Driver, Monitor and Scoreboard are the basic components of the Verification Environment. This Paper describes the basic Write operation to the SDRAM is Verified to check the functionality. This Operation is performed using System Verilog and Modelsim 6.3f. The Address and the Data size is 32bits and 8bit Memory Model is used to perform this operation.

Other Details

Paper ID: IJSRDV2I3101
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 242-244

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