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Verification of USB 2.0 Functional Core

Author(s):

PARTH R. ZALAWADIA , C-DAC,GTU PG SCHOOL; PARTH R. ZALAWADIA, GTU PG SCHOOL

Keywords:

Verification Environment, System Verilog, USB 2.0

Abstract

A verification environment to verify USB 2.0 Functional core using System Verilog is implemented in this paper. The verification IP can be reused to verify any USB protocol. Verification Environment is built to check the behaviour of DUT and to check whether we meet desired functionality of the core so that we can cover all the aspects of the design during verification. Verification of UTMI, Protocol Layer, Wishbone Interface and Memory Arbiter block is implemented in this paper. The Simulation Results are generated using QuestaSim 10.0b.

Other Details

Paper ID: IJSRDV2I3110
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 253-256

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