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Design Of An Optimized Full Adder And Ripple Carry Adder Using Reversible Logic.

Author(s):

Vishal Shankarrao Muley , VIT University; Anchu Tom, VIT Uinversity; Dr. Vigneswaran.T, VIT University

Keywords:

Reversible logic, Fredkin gate, 4 Bit BCD adder power consumption and CMOS full adder.

Abstract

the full adder is the basic block building that widely used in digital circuits such as the ALU and multiplier. One of the most promising technologies in designing low power circuits is reversible logic or computing. In the VLSI design of today’s circuits suffered from power consumption which leads to power dissipation in the circuits. To reduce the power dissipation in circuits, reversible logic is used. There are different types of logic gates are used to minimize the power dissipation and chip area such as NOT gate, Controlled NOT gate, Controlled Controlled NOT gate and Fredkin gate. In this research work some basic circuitry such as full adder and ripple carry adder with 45nm technology are highlighted.The proposed design is compare CMOS full adder and 4 bit Ripple carry adder with time delay and power dissipation. Power consumption is reduced 70% compared to conventional full adder and the time delay of the circuit is 19.88 nsec and 19.78 nsec for sum and carry respectively.

Other Details

Paper ID: IJSRDV2I3188
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 992-995

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