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Design and Analysis of a Full Adder Circuit using XOR and AND gates pass transistors and transmission gates


Sonam Tripathi , GBU, Greater Noida; R.B. Singh, GBU, Greater Noida


Full adder, Low operating power, High computing speed, pass transistors


This paper presents a complex full adder design having higher computing speed, lower operating voltage and low power consumption as these all are requirements of a VLSI design system. The proposed full adder design makes use of low power designs such as XOR and AND gates pass transistors and transmission gates. The simulation results are matched with the conventional cell by standard implementation. In this circuit design power consumption is done upto 40% by an addition. As the word length of the adder decreases the power consumption decreases significantly. We describe that how efficiently XOR and AND gates are realized to a general full adder circuit based on a pass transistor logic. The simulation results are compared with the standard simulation of the tool proposed in the project.

Other Details

Paper ID: IJSRDV2I3207
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 61-62

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