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Performance Analysis of a High speed and power efficient Full Adder at 65nm

Author(s):

Sonam Tripathi , GBU, Greater Noida; R.B. Singh, GBU, Greater Noida

Keywords:

CMOS technology, Gate Diffusion Technique, 8T full adder, 10T full adder, 11T full adder, 16T full adder

Abstract

In this paper presents an 8T full adder is designed to achieve lower average power and delay in comparison to 10T, 11T and 16T full adder designs. This design is carried out by the technique of Gate Diffusion i.e.GDI by reducing number of transistor counts which operates at very low voltage and offers a higher computation speed. The performance of the proposed full adder is evaluated by the comparison of the simulation result obtained in tanner tools using 65nm CMOS process technology with a supply voltage of 1.2V.

Other Details

Paper ID: IJSRDV2I3239
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 67-69

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