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Gaurav Sharma , Mewar University, Chittorgarh (Raj)


MIPS, RISC ,ALU, Memories, datapath ,FPGA.


in this paper includes the designing of low power 16-Bit MIPS RISC processor and modeling of its components using Verilog HDL. The implementation strategies have been borrowed from most popular MIPS architecture up to certain extent. The instruction set adopted here is extremely complex that gives an insight into the kind of hardware which should be able to execute the set of instructions properly. Along with sequential and combinational and sequential building blocks of NON- pipelined processor such as adders and registers more complex logics i.e. ALU, Datapath and Memories had been designed and simulated in Xilinx and modelsim. The modeling of ALU which has been done in this project is fully structural starting from adders and basic gates. Complex blocks have been modeled using behavioral approach i.e. Memories, datapath, whereas simple blocks i.e. Adders and subtract had been done through structural and mixed approach. The tools which had been used throughout the project work are Xilinx and active HDL (Digital Simulation), for synthesis purpose the targeted FPGA device technology was ALTERA, Cyclone, and EP1C6Q240C. A simple sequential block’s performance and figure of merits were observed under the constraints clock frequency: 50 MHz and DRT: 5ns.

Other Details

Paper ID: IJSRDV2I3324
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 628-629

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