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A Review on Power Reduction Technique for VLSI Designs


Dharmishtha Thakorbhai Patel , HGCE, VAHELAL; Patel Priyanka Sumantrai, SVIT, VASAD


Power reduction, low power, optimization, digital designs.


Low power has emerged as a necessity in portable electronics and communication devices. As a result, power dissipation has become an important design parameter for digital circuit designs. In this paper a survey is made regarding some existing techniques for power optimization in CMOS designs. Power optimization at logic and circuit levels is considered.

Other Details

Paper ID: IJSRDV2I3450
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 1348-1351

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