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Design, Verification and Physical Designing of FCFS Arbiter


Saurin Shah , M.E. in VLSI and Embedded Systems Design; Pankaj Chavda, M.E. in VLSI and Embedded Systems Design; Harshil Gajjar, M.E. in VLSI and Embedded Systems Design


Arbiter, Arbitration Scheme, FCFS, Verilog, SystemVerilog, Synopsys


In an environment where multiple masters and multiples slaves are used only one master can access the bus at a time for transaction over bus. Due to this, a mechanism is required which allows a single master to access the bus. This is accomplished by an electronic devise named as 'Arbiter’. Arbiter allocates access to shared resources. Based on priory different arbitrations schemes are required like Fair scheme, Round Robin scheme, Priority Based scheme, First Come First Serve scheme etc. Here a complete ASIC flow of First Come First Serve Arbiter is explained. Designing is done using Verilog, verification is performed using SystemVerilog and physical designing is shown. For complete process Synopsys tools are used.

Other Details

Paper ID: IJSRDV2I3481
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 1451-1453

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