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MODELLING OF AMBA AXI4 PROTOCOL

Author(s):

GURUPRASAD HEGDE , BMS COLLEGE OF ENGINEERING; Bharath B, BMS COLLEGE OF ENGINEERING; DARSHAN G M, BMS COLLEGE OF ENGINEERING; GNANESH G, BMS COLLEGE OF ENGINEERING

Keywords:

Shrinking process technologies , integrated circuits , AMBA AXI4 protocol, Verilog hardware description language, XILINX ISE simulation tool.

Abstract

Shrinking process technologies and increasing design sizes have led to highly complex billion-transistor integrated circuits (ICs). As a consequence, manufacturers are integrating increasing numbers of components on a chip. The need for high performance applications is driving the requirement for a new age of on chip communication infrastructure. On-chip bus organized communication architecture is among the top challenges in CMOS SoC technology due to rapidly increasing operation frequencies and growing chip size. This project is developed with the objective of enabling data transactions on SoC bus using AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are obtained using XILINX ISE simulation tool. The operating frequency is set to 250MHz. Four test cases are run to perform multiple read and multiple write operations. The architecture developed here is not the ultimate solution. Here we had made an attempt to know about AMBA AXI protocol and developed an interconnect design for multi-masters and multi-slaves.

Other Details

Paper ID: IJSRDV2I3603
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 1413-1416

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