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Low Power Pipelined RISC Processor :A Review

Author(s):

PRIYANKA TRIVEDI , GALGOTIAS UNIVERSITY; RAJAN PRASAD TRIPATHI, AMITY SCHOOL OF ENGINEERING

Keywords:

RISC, Pipeline, low power.

Abstract

Reduced Instruction Set Computing or RISC is design strategy predicated on the CPU design strategy. Pipelining is the concept of overlapping of multiple Instructions during execution time. Pipeline is work on the task function it can splits one task into multiple subtasks. This paper is a fixated on pipelining concepts and the low power techniques which are required for the RISC CORE Processor .low power techniques avail to reduce power and heat dissipation and lengthen the battery life.

Other Details

Paper ID: IJSRDV2I4156
Published in: Volume : 2, Issue : 4
Publication Date: 01/07/2014
Page(s): 526-528

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