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Reusable Verification Environment :Case Study SPI

Author(s):

Ripalkumar Patel , U. V. Patel college of Engineering, Ganpat University; Kavankumar Pandya, U. V. Patel college of Engineering, Ganpat University

Keywords:

SPI interface protocol, Master VIP , VCS.

Abstract

This project paper introduce with uniform verification environment using system Verilog as well as gives appropriate direction about reusability of verification environment’s components. This project paper divides with five sections. First section contains overview of SPI interface protocol. Second section is about physical interface for SPI protocol. Third section leads towards verification environment using system Verilog and over view about verification components. Fourth section is about Master VIP using reusability of environment’s components of SPI protocol with simulation results and coverage report using VCS. Fifth section is about Slave VIP using reusability of environment’s components of SPI protocol with simulation results and coverage report using VCS.

Other Details

Paper ID: IJSRDV2I4178
Published in: Volume : 2, Issue : 4
Publication Date: 01/07/2014
Page(s): 578-581

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