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Design and Analysis of 2:1 Multiplexer Using Low Power Adiabatic Technique and its Application in Nibble Multiplexer


Priyanka Grover , JCDMCOE; Veena Rani, JCDMCOE


Adiabatic Logic, 2:1 Multiplexer, PFAL, VLSI, T-Spice, Mux.


The power consumption and delay optimization has been the main concerns for the VLSI technology. In this paper we have proposed a new adiabatic circuit technique using diode connected transistors. The technique emphasizes on reduction of power by lowering the non-recoverable power consumption in adiabatic circuits. The technique achieves full adiabatic operation by providing separate charging and discharging paths. The PMOS devices provide the charging path while the diode connected NMOS devices provide low resistance discharge path which helps in reduction of power dissipation in the circuit. The paper compares the different logic style 2:1 multiplexes like CPL, EEPL and PFAL with the proposed design (ADDL) in terms of power and delay. The power consumption and delay is reduced up to a sufficient level with the help of new adiabatic logic technique. Nibble multiplexer is also designed using proposed logic. All the simulations have been performed at 90nm technology on Tanner EDA tool version 14.11.

Other Details

Paper ID: IJSRDV2I5033
Published in: Volume : 2, Issue : 5
Publication Date: 01/08/2014
Page(s): 84-87

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