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Verification of Four Port Router For NOC


G.Srinivasa Reddy , Vathsalya Institute of science and technology; Ch.Swathi, Vathsalya Institute of science and technology; B.Shirisha, Vathsalya Institute of science and technology


Network-on-Chip, Simulation Router, FIFO, FSM, Register blocks


The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the four port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualify the IP for Synthesis an implementation. This Router design contains three output ports and one input port, it is packet based Protocol. This Design consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized timemultiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.

Other Details

Paper ID: IJSRDV2I8072
Published in: Volume : 2, Issue : 8
Publication Date: 01/11/2014
Page(s): 172-174

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