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CMOS Dynamic Logic: A Review

Author(s):

Suminder Kaur , JCDMCOE; Er. Rajni, JCDMCOE

Keywords:

CMOS Dynamic Logic, OR Dynamic Logic, Domino Logic, Noise Tolerance

Abstract

In this paper a review of the dynamic logic circuit design has been done as these circuits are used due to their high performance, high speed and less number of transistors in the circuit. The number of required transistors is lesser than the CMOS logic style. The OR dynamic logic style is not applicable as it has low noise tolerance at the dynamic stage which can change the output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and has less capacitance at the output node.

Other Details

Paper ID: IJSRDV2I8081
Published in: Volume : 2, Issue : 8
Publication Date: 01/11/2014
Page(s): 60-61

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