Low Power Pulse Triggered Flip Flop with Modified Conditional Pulse Enhancement Scheme |
Author(s): |
| Resham Singh , YMCA University of Science & Technology, Faridabad, Haryana; Naveen Singroha, YMCA University of Science & Technology, Faridabad, Haryana; Rohit Rohila, YMCA University of Science & Technology, Faridabad, Haryana; Bal Krishan, YMCA University of Science & Technology, Faridabad, Haryana, YMCA University of Science & Technology, Faridabad, Haryana |
Keywords: |
| Flip-Flop, Low Power, Pulse-Triggered FF |
Abstract |
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In this work, a low-power pulse-triggered flip-flop (FF) with modified conditional pulse enhancement scheme is proposed. The proposed design fulfills the discharging problem using the pulse generation control logic, an AND function, which facilitates a faster discharge operation. A two-transistor AND gate design is used to reduce the circuit complexity and modified conditional pulse-enhancement technique is devised to speed up the discharge along the critical path when circuit required. Modified scheme is used different approach to provide delay in the CLK. As a result, transistor sizes in pulse-generation circuit and delay inverter can be reduced for power saving. All simulation results are based on using CMOS 90-nm process technology at 500MHz clock frequency. Its maximum power saving against conditional pulse FF is up to 8.85%. |
Other Details |
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Paper ID: IJSRDV3I1516 Published in: Volume : 3, Issue : 1 Publication Date: 01/04/2015 Page(s): 1150-1152 |
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