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Power Gating Based Low Power 32 Bit BCD Adder Using DVT

Author(s):

R.Santhiya , Sri Eshwar College of Engineering,Coimbatore; T.ThamaraiManalan, Sri Eshwar College of Engineering,Coimbatore

Keywords:

Binary coded decimal (BCD), ElectronicDesign Automation (EDA), Gate Diffusion Input (GDI), DVT (Dual Voltage)

Abstract

Minimizing power dissipation during the VLSI design flow increases life time and reliability of the circuit. Numerous technologies for the design of low power VLSI circuits are reported where the dominant factor of power dissipation is caused by switching activity and large circuit area. The techniques used to reduce the power consumption and leakage power in a circuit is DVT and Power Gating. The GDI technique consumes low power which is used to design a full adder in a circuit. The simulation is done by using TANNER (EDA) tool and the result is compared with other BCD adder circuits. The average power consumed by the BCD adder is 1.384 μw and the frequency is 200 MHZ with 1v supply voltage.

Other Details

Paper ID: IJSRDV3I2632
Published in: Volume : 3, Issue : 2
Publication Date: 01/05/2015
Page(s): 802-805

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