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Low Power Reduction Technique in VLSI

Author(s):

Sima Baidya , WBUT; Arindam Chakraborty, WBUT

Keywords:

low power, sub-threshold, Delay

Abstract

Power and performance have become the predominant concern for chip designers in deep submicron technology due to the continuous scale down of the device for satisfying the Moore’s law which state that the number of transistor per chip will be double in every eighteen month. When the channel length shrinks, the absolute value of threshold voltage become smaller due to the reduced controllability of the gate over the channel depletion region by increasing charge sharing from source/drain which results in the increase in sub threshold leakage current exponentially, so the static power dissipation increased. In the deep submicron technology CMOS power dissipation plays a vital rule. Various comprehensive studies on leakage power minimization technique have been studied in this paper focusing on circuit performance parameter.

Other Details

Paper ID: IJSRDV3I30924
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 3419-3422

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