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FPGA Implementation of AES Based on MIPS

Author(s):

Raval Mitesh M. , Hasmukh Goswami College of Engineering; Dharmedra B. Patel, Hasmukh Goswami College of Engineering

Keywords:

AES (advance encryption standard), MIPS, Pipelining, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field programmable gate array)

Abstract

Achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. For the security of data, various solutions algorithms were proposed. Use such an encryption methods such as DES, 3DES and AES etc. The AES also known as the Rijndael algorithm was selected as a Standard by National Institute of Standards and Technology (NIST). Encryption algorithms are used to ensure security of transmission channels. In this paper two different architectures i.e. AES and Pipelined AES have been designed in VHDL. The comparison is being done between the Basic AES and Fully Pipelined AES algorithm. It will make it faster and secure compare to software implementation.

Other Details

Paper ID: IJSRDV3I31064
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 1680-1683

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