High Impact Factor : 4.396 icon | Submit Manuscript Online icon |

Low Area & Power Decimal Addition with Improved Speed using LING Adder Architecture

Author(s):

T.Sindhu , Velalar college of engineering and technology; P.Brindha, Velalar college of engineering and technology

Keywords:

Decimal computer arithmetic, Speculative decimal addition, Combined binary/decimal-add/sub, Carry-select correction

Abstract

Adder plays a major role in electronics, not only in computers but also in many types of digital systems in which the numeric data are processed. In several applications like monetary and business computation requires decimal arithmetic operator to directly process decimal data for accurate computations and hence adder must perform decimal addition. Faster decimal addition can be performed with an embedded world-wide binary adder, leading to considerable hardware sharing with binary input unit. Carry-select technique for the decimal adders can be improved by computing pairs of corrective carry out bits for all decimal positions in parallel. This was performed by the quaternary parallel prefix network and the selection is based on corresponding positional carry-in bits. Carry select sum and Carry select correction block with reduced area than the previous structures is used in this fused binary/decimal adder. Area improvement will reduce the cost and power consumption of the system. Ling adder structure is used in the prefix network for speed improvement.

Other Details

Paper ID: IJSRDV3I31119
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 3237-3240

Article Preview

Download Article