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Design and Simulation of Optimized Color Interpolation Processor for Image and Video Application


Rashmi Betina , CMRIT; Naveen Kumar G. N, CMRIT


MATLAB Simulink®; block level design; chip area; power consumption


In this project, the design of an optimized structural based interpolation processor is proposed. This proposed system provides the block level design in MATLAB Simulink® workspace. This block level design reduces the complexity of design. The Verilog code is generated using the Xilinx system generator automatically based on the design in the MATLAB Simulink® workspace which reduces the human errors. The architecture of the proposed system is highly efficient. The chip area and the power consumption of the design are highly optimized in the proposed system. The number of gate counts and the design utilities are highly reduced.

Other Details

Paper ID: IJSRDV3I31474
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 3256-3260

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