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Implementation of High Speed Single Precision Floating Point Multiplier

Author(s):

Reshmashree M S , DR. AMBEDKAR INSTITUTE OF TECHNOLOGY, BANGALORE; Meenakshi L Rathod, DR. AMBEDKAR INSTITUTE OF TECHNOLOGY, BANGALORE

Keywords:

IEEE754, Xilinx 12.4, Algorithm

Abstract

This paper presents design of a high speed multiplier for IEEE754 single precision floating point numbers. In all microprocessors, industrial area and applications involving arithmetic operation, it is required that the operations are carried out at a faster rate. Thus, to increase the speed of the multiplication operation, Dadda algorithm is used. The basic modules are designed using Verilog language and implemented using Xilinx 12.4 ISE software and the same is simulated using isim simulator. The Dadda multiplier is designed using Carry lookahead adder and the results are verified to achieve higher speed criteria.

Other Details

Paper ID: IJSRDV3I31499
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 3351-3352

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