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Efficient Interleaver Design for MIMO-OFDM based Communication Systems on FPGA


Shridevi Kenganal , adichunchanagiri institute of technology, chikkamagaluru; Dr.M.A.Goutham, adichunchanagiri institute of technology, chikkamagaluru




A memory-efficient and faster interleaver implementation technique for MIMO-OFDM communication systems on FPGA. The IEEE 802.16 standard is used as a reference for simulation, implementation, and analysis. The main aim is to design interleaver for various modulation schemes like BPSK,QPSK,16QAM,64 QAM. The interleaver plays a important role in improving performance of EFC codes.The interleaver design is divided in to two parts as address generator and interleaver memory.The finite state machine baesd interleaver shows the better performance like maximum frequency and FPGA resources utilization as compared previous FPGA techniques. Interleaver is implemented using xilinix ISE and simulation results are presented The hardware model is implemented on FPGA kit spratan 3.

Other Details

Paper ID: IJSRDV3I31516
Published in: Volume : 3, Issue : 3
Publication Date: 01/06/2015
Page(s): 3304-3306

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