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A Review on Pulse Triggered Flip-Flop with Conditional Pulse Enhancement Scheme


Amita , Indus Institute of Engineering and Technology, Kinana, Jind, Haryana - 126102; Sunaina Singroha, Indus Institute of Engineering and Technology, Kinana, Jind, Haryana - 126102


Flip-Flops, conditional pulse enhancement, low power, pulse triggered


In this review work, a low-power pulse-triggered flip-flop (PTFF) design is described. Conventional proposed Flip-Flop (FF) has two new features. First one, the pulse generation control logic and an AND function, is removed from the critical path to facilitate a faster discharge operation. To reduce the circuit complexity a simple two-transistor AND gate design is used. Second one, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in pulse-generation circuit and delay inverter can be reduced for power saving. Various post layout simulation results based on CMOS 90-nm technology reveal that the conventional proposed design features the best power-delay-product performance in three FF designs under comparison.

Other Details

Paper ID: IJSRDV3I41036
Published in: Volume : 3, Issue : 4
Publication Date: 01/07/2015
Page(s): 3331-3333

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