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Analysis and Modification of D Flip Flop Using Different Techniques

Author(s):

Hardeep Kaur , Baba farid college of engineering and technology,bathinda; Er. Swaranjeet Singh, Baba farid college of engineering and technology,bathinda; Sukhdeep Kaur, Baba farid college of engineering and technology,bathinda

Keywords:

Low Power, Propagation Delay, CMOS, GDI, GDI MUX, TG, POWER PC, C2MOS & TSPC, D Flip flop

Abstract

Low power design has become one of the primary focuses in both analogue and digital VLSI circuits. The pertinent choice of flip flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance speed of circuits. This paper enumerates low, high speed design of D flip flop .It presents various techniques to minimize the power consumption of CMOS circuits. In this D flip flop is implemented using Static CMOS, CCMOS, GDI, GDI MUX, POWER PC,TG and TSPC Techniques. The simulation is done on TANNER EDA Tool at 180nm &130nm Technologies.

Other Details

Paper ID: IJSRDV3I60302
Published in: Volume : 3, Issue : 6
Publication Date: 01/09/2015
Page(s): 811-816

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