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A Novel Approach to Design and Implement the High Efficiency Multiplier


Neha Jassi , SDDITE; Arti Goel, sddiet


DADDA Multiplier, Brent Kung Adder, Ripple Carry Adder, Single Precision


This paper describes the single precision floating point multiplier. Floating-point numbers are widely adopted in many applications due to their dynamic representation capabilities. Floating point numbers represents real numbers in binary format. This paper presents a high speed binary floating point multiplier based on dadda algorithm with brent kung adder. To consume less area addition is done using brent kung adder replacing ripple carry adder. The design achieves frequency of 775.705 MHz with 862 slice area compared to existing floating point multipliers. The floating point multiplier is developed to handle the underflow and overflow cases. The multiplier is implemented using Verilog HDL and it is targeted for Xilinx Virtex-5 FPGA and design is simulated using Modelsim.

Other Details

Paper ID: IJSRDV3I60399
Published in: Volume : 3, Issue : 6
Publication Date: 01/09/2015
Page(s): 1187-1190

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