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Design and Implementation of Power and Area Optimized 16-Bit 5T SRAM Array using Cadence 90NM Technology

Author(s):

Maruti Lamani , VESVESHVARAYA TECHNOLOGICAL UNIVERSITY ,BELAGAVI KARNATAKA INDIA; Dr.Meghana Kulkarni, VTU,BELAGAVI, KARNATAKA; Umashree M Sajjanar, VTU,BELAGAVI, KARNATAKA

Keywords:

SRAM, CMOS, Cadence

Abstract

As the technology scaling goes on increasing, reduction in power consumption and over all power management on chip are main challenges for any size below 100nm due to increased complexity and area reduction. Semiconductor memories are most important subsystem of modern digital systems. Many advance processors now have on chip instructions and data memory using SRAMs. Thus, improving the power efficiency of a SRAM cell is critical to the overall system power consumption. This project is based on the design of a CMOS Five-transistor SRAM cell (5T SRAM cell) for very high density and low power applications. This paper investigates the effectiveness of 5T SRAM circuit design technique along with power consumption and chip density analysis. Simulation and analytical results show that proposed cell has correct operation during read/write mode. The new cell size is 21.66% smaller than a conventional 6T SRAM cell using same design rules with no performance degradation. The new 5T SRAM cell contains 68.84% less power consumption with respect to the 6T SRAM cell and also the average power consumption of 16 bit 5T SRAM array has been reduced by 69.17% when compared to 16-bit 6T SRAM Array using cadence 90nm technology.

Other Details

Paper ID: IJSRDV3I60412
Published in: Volume : 3, Issue : 6
Publication Date: 01/09/2015
Page(s): 772-776

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