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Design of a Self-Test Unit for Microprocessor in On-Line Scenario using Verilog


Swathi G Gudadawar , VTU, JNANASANGAMA , BELAGAVI; Rohit B Malagi, VTU; Dr. Meghana Kulkarni, VTU




As the technology grows day by day, testing of an embedded microprocessor in a SoC environment is becoming more complex. The design is explicitly focused on achieving testing speed and less area of the test program in a SoC. In this paper, a proposed technique which presents an innovative solution to the SoC testing. Here, architecture for the embedded microprocessor testing has been designed by using Verilog language. The proposed architecture restricts the processor to execute a test sequence during the normal operation in an online scenario, to save the execution time. Instead, it is connected to the system bus like a normal memory core to perform the test operation. The design saves execution time and uses less area for its testing unit. Nowadays, the Software-based Self-Test (SBST) and Built-in Self-Test (BIST) techniques are very popular in testing Microprocessors to reduce the testing challenges. But, SBST technique is the most preferable one in the on-line scenario. The Proposed architecture which combines BIST and SBST principle gives the perfect system to reduce the testing time in on-line scenario. The benefits of using this architecture is that it doesn’t require a memory of the system to store the data, which tries to maintain IP of the processor core and saves the execution time. The proposed solution is designed and simulated using Xilinx 13.1.

Other Details

Paper ID: IJSRDV3I60532
Published in: Volume : 3, Issue : 6
Publication Date: 01/09/2015
Page(s): 1145-1150

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