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A High Speed Full Adder Circuit using 3 Transistor XOR Gates for Arithmetic Operations of VLSI System

Author(s):

Richa Baranwal , Madan Mohan Malaviya University of Technology, Gorakhpur; Vimal Kumar Mishra, Madan Mohan Malaviya University of Technology, Gorakhpur; Dr.R.K. Chauhan, Madan Mohan Malaviya University of Technology, Gorakhpur

Keywords:

CMOS, Enhancing Speed, Full Adder, MGDI, Transistor Count Minimization and XOR gate

Abstract

The necessities to obtain better speed, this paper list to a change in parameter of full adder circuit that has been proposed by using 3T XOR gate combining CMOS with pass transistor logic. The design that has been given shows a significant improvement in propagation delay constrain. The proposed adder gives better propagation delay in comparison with the previously existing reference design. The 50nm technology has been used to investigate the performance of 8T full adder circuit and the complete design is simulated with the help of LTSPICE.

Other Details

Paper ID: IJSRDV3I60630
Published in: Volume : 3, Issue : 6
Publication Date: 01/09/2015
Page(s): 1126-1128

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