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An Optimized Implementation of CSLA for 32-Bit Mac using VHDL

Author(s):

Bhavya Sree Kotte , Srinivasa institute of technology & science; S Saleem Malik, Srinivasa institute of technology @science

Keywords:

Low power, Multiplier and Accumulator, Carry Save Adder, Carry Look-ahead Adder, Carry Select Adder

Abstract

This project deals with the comparison of the VLSI design of the carry select adder (CSLA) based 32-bit multiplier. Both the VLSI design of multiplier multiplies two 32-bit values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay some time for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation. With the growing importance of electronic products in day-to-day life, the need for portable electronic products with low power consumption largely increases. In this paper, Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) is being designed. In the same MAC architecture design in final adder stage of partial product unit the carry save adder (CSA), carry select adder (CSLA) are also used instead of CLA to compare the power and performance. These MAC designs were simulated and synthesized using Xilinx 13.2. These multipliers are implemented using Xilinx ISE, simulation diagrams are viewed through Xilinx ISE. The simulation result shows that the MAC design with CLA has area reducing by 15%, 35% reduction is seen in power analysis and 4times increase of delay analysis.

Other Details

Paper ID: IJSRDV3I70084
Published in: Volume : 3, Issue : 7
Publication Date: 01/10/2015
Page(s): 107-110

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