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Implementation Report For Fir Filter Design Based Upon Rounded Truncated Constant Accumulation

Author(s):

Ashwini v. Joshi , MCERC College Nasik; Prof. R.S.Khule, E &TC Dept. MCERC College Nasik

Keywords:

Digital Signal Processing (DSP), Faithful Rounding, Finite Impulse Response (FIR) Filter, Truncated Multipliers, VLSI Design

Abstract

In proposed system Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. The optimization of bit width and hardware resources without sacrificing the frequency response and output signal accuracy. Multiple constant multiplication/accumulation in a direct FIR structure is implemented in direct form structure using a developed version of truncated multipliers which helps to reduce bit width. Dadda algorithm is adapted to reduced tree of partial product bits. Comparisons with previous FIR design approaches show that the proposed design gives more area and power efficient results.

Other Details

Paper ID: IJSRDV3I70139
Published in: Volume : 3, Issue : 7
Publication Date: 01/10/2015
Page(s): 535-537

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