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Improved Design of MOD-8 Synchronous UP/DOWN Counter Using Reversible Gate

Author(s):

Abhijit Dey , NSHM Knowledge Campus Durgapur; Shashank Kumar Singh, NSHM Knowledge Campus Durgapur; Heranmoy Maity, NSHM Knowledge Campus Durgapur

Keywords:

Reversible Logic, Quantum Cost, Constant Input, Garbage Output, Synchronous Counter

Abstract

The Reversible logic synthesis techniques will definitely be a necessary part of the long-term future of computing due to its low power dissipating characteristic. Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Today, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design of circuits. In this paper we proposed the design of MOD-8 synchronous up/down counter having reduced quantum cost, constant inputs and less number of gates to implement it using existing reversible gates.

Other Details

Paper ID: IJSRDV3I70460
Published in: Volume : 3, Issue : 7
Publication Date: 01/10/2015
Page(s): 787-790

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