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Design of 4 Bit Johnson Counter Using Reduced Number of Reversible Logic Gates


Heranmoy Maity , NSHM Knowledge Campus Durgapur; Shashank Kumar Singh, NSHM Knowledge Campus Durgapur; Abhijit Dey, NSHM Knowledge Campus Durgapur; Anu Debnath, NSHM Knowledge Campus Durgapur


Reversible Logic, Quantum Cost, Constant Input, Garbage Output, Delay, Johnson Counter


Over the last few decade reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter with reduced number of reversible gates and derived with constant inputs, garbage output and number of gates to implement it.

Other Details

Paper ID: IJSRDV3I70471
Published in: Volume : 3, Issue : 7
Publication Date: 01/10/2015
Page(s): 778-779

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