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Power Reduction for Pulse Triggered Flip Flop Using Sleep Transistor


Jagadeesh Kumar , sitams college; G.balakrishna, sitams college


Pulse Triggered Flip Flop, Low Power, Flip Flop


The flip flop technologies is an essential importance design of VLSI design circuits for low power ,high speed and high performance .In this thesis used low power flip flop is designed by pulse generator and latch ,low power flip flop design featuring explicit type pulse triggered flip flop structure and a modified true single phase clock depends on a signal feed through logic is presented .It is need to reduce power dissipation in both clock distribution and flip flop .Here some kinds of pulse triggered was designed, the proposed design improves discharging problem and dynamic and leakage power using sleep transistor technology and achieve better speed and power than convectional flip flop.

Other Details

Paper ID: IJSRDV3I80041
Published in: Volume : 3, Issue : 8
Publication Date: 01/11/2015
Page(s): 66-69

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