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Design and Simulation of Pipelined 32 Point FFT using Radix 2 Algorithm


Rutuja R.Taksande , BDCOE; Prof. M. N. Thakare, BDCOE; Prof. G. D. Korde, BDCOE


Fast Fourier Transform, Floating Point Complex Multiplier, XILINX ISE 14.5i, VHDL


The Fast Fourier Transform (FFT) is one of the important operations in field of digital signal processing. Fast Fourier Transform is an algorithm which computes the Discrete Fourier Transform of an input sequence. This paper gives design of the Fast Fourier Transform (FFT) based on Decimation-In-Time (DIT) domain and Radix-2 algorithm .The input of Fast Fourier transform has been given by using a test bench code and output has been displayed using the waveforms son the Xilinx Design Suite 14.5.i.This Paper also includes design, synthesis and simulation of Vedic 32-bit Floating Point Complex Multiplier and 32 point Pipelined FFT. The coding has been done in VHDL whereas design, synthesis and simulation has been done using XILINX ISE 14.5i tool. The delay obtained for Vedic 32-bit Floating Point Complex Multiplier and 32 point Pipelined FFT is 36.356 ns and 24.801ns respectively .The synthesis and simulation results show that the computation for calculating the 32-point Fast Fourier transform is efficient in terms of speed and power.

Other Details

Paper ID: IJSRDV4I120271
Published in: Volume : 4, Issue : 12
Publication Date: 01/03/2017
Page(s): 459-461

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