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A Novel Approach for Improving the Power Efficient and Metastability Resistant Resilient Circuit


D.Maheswari , Vivekanandha college of engineering for women; P.Nagarajan, Vivekanandha college of engineering for women; C.M.Kalaiselvi, Vivekanandha college of engineering for women; C.Dhivya, Vivekanandha college of engineering for women


Dynamic voltage scaling (DVS), Edge detector, Error Resilient Flipflop, Resilient circuits


In this paper, a meta stability resistant caution flipflop (FF) is proposed, which consists of an edge detector, a caution window generator, and a caution detector along with a timing error resilient flip-flop. The delayed data are monitored during the caution window to flag a warning signal before the data enter the erroneous zone. In this scheme, the caution window is independent of input clock frequency and hence is suitable for frequency scaling application. The proposed flip-flop design routinely corrects timing errors and therefore minimizes the performance degradation due to variations.

Other Details

Paper ID: IJSRDV4I20387
Published in: Volume : 4, Issue : 2
Publication Date: 01/05/2016
Page(s): 998-1002

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