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User Controlled, Hardware Approach to Multi Byte Convolutional Encoder


Bhaskar Nandy , Heritage Institute of Technology


FPGAkitBasys2board;Xilinx ISE design suite 14.1;MATLAB & SIMULINK verR2013a; MATLAB Communication Tool box; Code Rate; Constraint length; Generator Polynomial; Poly2trellis structure


This paper focuses on Field Programmable Gate Array (FPGA) which is designed to user operate as an non systematic, convolutional encoder with its best performance configuration with a code rate of 0.5 and constraint length 3. BPSK is modulation technique which is implemented for this system which is analyzed to be the best modulation technique so far. Errors do occur randomly in any communication system is the most concerning factor since it makes the system vulnerable to security threats. A system being designed to prevent such treats by detecting, amending the errors as far as possible. Convolutional codes is a supreme forward error correcting (FEC) code with a least code rate which serves this purpose.

Other Details

Paper ID: IJSRDV4I20844
Published in: Volume : 4, Issue : 2
Publication Date: 01/05/2016
Page(s): 927-930

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