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Low Cost Design of MOD-8 Synchronous UP/DOWN Counter Using Reversible Logic Gate

Author(s):

Heranmoy Maity , NSHM Knowledge Campus Durgapur, India; Arindam Biswas, NSHM Knowledge Campus Durgapur, India; Anup Kumar Bhattacharjee, National Institute of Technology Durgapur, India

Keywords:

Reversible logic gate, Counter, Constant input, Garbage output, Delay

Abstract

The Reversible logic synthesis technique is most important part of the long-term future of computing due to its low power dissipating characteristic. Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Today, reversible logic circuits have substantial attention in improving the field of nanotechnology, quantum computing, and low power design of circuits. In this paper we proposed the design of low cost MOD-8 synchronous up/down counter with reduced number of reversible logic gate, constant inputs and garbage outputs using existing reversible gate.

Other Details

Paper ID: IJSRDV4I40035
Published in: Volume : 4, Issue : 4
Publication Date: 01/07/2016
Page(s): 9-11

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