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A Low Power Dynamic Latched Double Tail Comparator: A Review


Manish Kumar , Indus Institute of Engineering and Technology, Kinana; Kapil Sachdeva, Indus Institute of Engineering and Technology, Kinana


ADC, Comparator, Low Power Design, Kick Back Noise


This paper presents a review on the low power dynamic latched double tail comparator designed on Tanner EDA. A new dynamic latched comparator which shows lower power consumption and high speed than the conventional dynamic latched comparators can be designed as per the rising demand of low power and high performance circuits in VLSI.

Other Details

Paper ID: IJSRDV4I40209
Published in: Volume : 4, Issue : 4
Publication Date: 01/07/2016
Page(s): 183-185

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