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Design of High Performance Compressor based Urdhwa Tiryakbhyam Multiplier


Mrunal Mahakale , G.H.R.A.E & T NAGPUR; R. W. Jasutkar, G.H.R.A.E & T NAGPUR


High Speed Multiplier, 4:2 Compressor, Vedic Mathematics, VHDL Code


In the new technology of VLSI, Communication and signal processing. there is an vast demand for the high speed and low area design. In this project we have designed compressor based multiplier, We introduced 4:2 Compressor replaced several half adder and full adder then reduced the complexity of circuit and addition to that by using vedic mathematics. There are 16 sutras in vedic multiplication in which “Urdhawa Tiryakbhyam” has been noticed to be the most efficient one in terms of speed. The multiplier is coded in VHDL and synthesis and simulation by using Xilinx ISE 13.1. Further the design multiplier compared with proposed multiplier in terms of delay and area.

Other Details

Paper ID: IJSRDV4I50488
Published in: Volume : 4, Issue : 5
Publication Date: 01/08/2016
Page(s): 874-877

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