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Data Encoding Techniques for Network on Chip Links


Nikhila Kamath , VTU PG center gulbarga


NoC, Data Encoding, Network Interface (NI)


As the VLSI circuits become denser, every element in the system gets complicated. With the increase in number of chips embedded on a core, the on chip communication subsystem becomes prominent. Shrinking VLSI technology to nanometer scale, the links of the network on chip dissipate more power. This power dissipation by the links starts to compete with the power dissipated by the other essential elements of the communication subsystem, namely, the network interfaces and routers. The dynamic power dissipation in network links is the major contributor to the power consumption in network on chip. This is due to the switching activity in the links. The self-switching and the coupling capacitance are the most important causes for the dynamic power dissipation. A set of three encoding techniques are proposed to minimize the switching activity in the links. The proposed scheme reduces the self-switching by seeing the switching transition, and then the cross coupling capacitance between the links is checked and verified that the power consumption is decreased at the links of the network interface (NI). The proposed schemes can be employed without any modifications to the link and router design. These schemes are tested for several inputs and the effectiveness of the scheme is verified by synthesizing the proposed design in Xilinx ISE which is coded in Verilog HDL and simulated in ISim simulator. FPGA implementation is done on Xilinx Spartan-3E kit. The proposed design controls power dissipation and the energy consumption without any considerable performance degradation and with a reduced amount of area overhead in the NI.

Other Details

Paper ID: IJSRDV4I60035
Published in: Volume : 4, Issue : 6
Publication Date: 01/09/2016
Page(s): 211-214

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