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Sum-of-Products & Parallel VLSI Transistor-Level by CMOS Logic Gates


Mr. N. Md. Bilal , Svr Engineering College Nandyal; Shasi Rekha Talari, Svr Engineering College Nandyal


sum-of-products (SOP) -parallel (SP), VLSI, Transistor-level, and CMOS logic gates


VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are strongly related to the number of transistors (switches). Hence, transistor arrangement optimization is of special interest when designing standard cell libraries and custom gates. Switch based technologies, such as CMOS, FinFET, and carbon nanotubes, can take advantage of such an improvement. Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver series–parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates.

Other Details

Paper ID: IJSRDV4I60507
Published in: Volume : 4, Issue : 6
Publication Date: 01/09/2016
Page(s): 988-989

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