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Implementation Field Programmable Gate Array Using Modified Distributed Arithmetic & Finite Impulse Response by Filter Reconfigurable

Author(s):

MR. N.MD. MOHASINUL HUQ , Svr Engineering College Nandyal; SUBBAMMA KALINGIRI, Svr Engineering College Nandyal

Keywords:

Modified Distributed Arithmetic (DA), Finite Impulse Response (FIR) Filter, Reconfigurable Implementation, Field Programmable Gate Array (FPGA), Look Up Table (LUT)

Abstract

In signal processing, a digital filter is a system that performs mathematical operations on a sampled, discrete-time signal to reduce/enhance certain aspects of that signal. A digital filter usually contains of an ADC to sample the input signal, it is continued by a microprocessor and the peripheral components such as memory to store data and filter coefficients etc. In some of the high performance applications, instead of using a general purpose microprocessor, FPGA or ASIC can be used for expediting operations such as filtering. One type of digital filter is FIR filter which is stable and gives linear phase response. For an Nth order FIR filter, the generation of each output sample takes N+1 MAC operations. Memory based structures are well-suited for many DSP algorithms, which includes multiplication with a set of coefficients which remains fixed. For this purpose, Distributed Arithmetic architecture is used in FIR filter. Distributed arithmetic is one way to implement convolution without the multiplier unit, where the MAC operations can be replaced by a series of LUT access and summations. LUT are the kind of logic that used in DRAM based FPGAs. It is mainly used in the applications like Software Defined Radio (SDR), Digital up/down converters, Multi-Channel filters where the coefficients are changed during the run time. Hence LUT’s are needed to be reconfigurable. This project achieves high-throughput by implementing the reconfigurable FIR filter using modified Distributed Arithmetic (DA) based approaches. For this implementation of reconfigurable FIR filter RAM based LUT’s are used, and the implementation of such LUT’s remains costlier. Thus a shared LUT design is proposed for reconfigurable FIR filter. Requirement of separate registers are eliminated by sharing the registers for different bit slices. Thus the DRAM based FIR filter reduces the number of bit slices. The proposed design is implemented in Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

Other Details

Paper ID: IJSRDV4I60508
Published in: Volume : 4, Issue : 6
Publication Date: 01/09/2016
Page(s): 990-993

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